1. Field of the Invention
This invention relates to an array substrate of a liquid crystal display and a fabricating method thereof, and more particularly to an array substrate of a liquid crystal display and a fabricating method thereof that is capable of increasing the electrostatic capacitance of a storage capacitor without any decrease of an aperture ratio to reduce flickers and to lessen the number of required processes.
2. Description of the Related Art
Generally, a liquid crystal display LCD controls a light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal pixels arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, there are provided a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal pixels. The pixel electrode is formed on a lower substrate by liquid crystal pixels, whereas the common electrode is formed on the entire surface of an upper substrate. Each pixel electrode is connected to a thin film transistor TFT used as a switching device. The pixel electrode together with the common electrode drives the liquid crystal pixel in accordance with data signals supplied through the TFT.
FIG. 1 is a plan view showing an array substrate of a conventional liquid crystal display, FIG. 2 is a sectional view of the array substrate of the liquid crystal display taken along the line “A-A′” shown in FIG. 1.
Referring to FIGS. 1 and 2, a lower substrate 11 of a liquid crystal display includes a TFT 28 located at the intersection of a data line 24 and a gate line 15n, a pixel electrode 33 connected to a drain electrode 25 of the TFT 28, and a storage capacitor 26 located at the overlapping area of the pixel electrode 33 and a previous gate line 15n-1.
The TFT 28 includes a gate electrode 13 connected to the gate line 15n, a source electrode 23 connected to the data line 24, and the drain electrode 25 connected to the pixel electrode 33 through a first contact hole 30a. Also, the TFT 28 further includes a gate insulating film 17 for insulating the gate electrode 13 from the source and drain electrode 23 and 25, and semiconductor layers 19 and 21 for defining a channel between the source electrode 23 and the drain electrode 25 by a gate voltage applied to the gate electrode 13. The TFT 28 responds to a gate signal from the gate line 15 to selectively apply a data signal from the data line 24 to the pixel electrode 33.
The pixel electrode 33 is positioned at a cell area divided by the data line 24 and the gate line 15n, and is made of a transparent conductive material having a high light transmissivity, such as indium tin oxide ITO, etc. The pixel electrode 33 is formed on a second protective layer 31 spread on the entire surface of the lower substrate, is electrically connected to the drain electrode 25 through the first contact hole 30a passing through first and second protective layers 27 and 31. Such a pixel electrode 33 generates a potential difference from a common transparent electrode (not shown) provided at an upper substrate (not shown) by a data signal applied via the TFT. By this potential difference, a liquid crystal positioned between the lower substrate 11 and the upper substrate rotates due to its dielectric anisotropy. In other words, the liquid crystal display changes the molecular arrangement of the liquid crystal cells in accordance with the voltage applied by the pixels, to display images or the like.
FIGS. 3 to 8 are sectional views showing by steps a conventional fabricating method of the liquid crystal display shown in FIG. 2.
Referring to FIG. 3, there are formed the gate electrode 13 and the previous gate line 15n-1 on the lower substrate 11. Aluminum Al or Copper Cu is deposited on the entire surface of the substrate 11 by a known deposition method such as a sputtering method, etc. and is then patterned to form the gate electrode 13 and the previous gate line 15n-1.
Referring to FIG. 4, a gate insulating film 17 is formed over the gate electrode 13 and the previous gate line 15n-1. Then an active layer 19 and an ohmic contact layer 21 are formed on the gate insulating film 17. In this step, an insulating material is entirely deposited to cover the gate electrode 13 and the gate line 15n-1 by a plasma enhanced chemical vapor deposition PECVD method, to form the gate insulating film 17. The active layer 19 and the ohmic contact layer 21 are formed by depositing two semiconductor layers on the gate insulating film 17 and patterning them. Herein, the active layer 19 is formed of amorphous silicon that is not doped with impurities. The ohmic contact layer 21 is formed of amorphous silicon that is extensively doped with impurities of N type or P type.
Referring to FIG. 5, the data line 24 and the source and drain electrodes 23 and 25 are formed on the gate insulating film 17. In this step, a metal is entirely deposited by a CVD technique or sputtering technique and then patterned to form the data line 24 and the source and drain electrodes 23 and 25. The source and drain electrodes 23 and 25 are patterned, and then the area of the ohmic contact layer 21 corresponding to the gate electrode 13 is patterned to expose the active layer 19. The area corresponding to the gate electrode 13 between the source and drain electrodes 23 and 25 in the active layer 19 becomes a channel. The data line 24 and the source and drain electrodes 23 and 25 are formed of chromium Cr or molybdenum Mo.
Referring to FIG. 6, the first protective layer 27 and a storage electrode 29 are formed on the gate insulating film 17. In this step, the first protective layer 27 are formed by depositing an insulating material on the gate insulating layer 17 with the thickness of 1˜2 μm to cover the source and drain electrodes 23 and 25. The first protective layer 27 is formed of an organic insulating material with a small dielectric constant such as acrylic organic compound, Teflon, benzocyclobutene BCB, Cytop, or perfluorocyclobutane PFCB.
The storage electrode 29 is formed by depositing a transparent conductive material on the first protective layer 27, and then patterning it. The storage electrode 29 is formed of indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or indium-tin-zinc-oxide (ITZO).
Referring to FIG. 7, the second protective layer 31 is formed on the first protective layer 27 and the storage electrode 29. The first to third contact holes 30a, 30b and 30c are provided through the first and/or second protective layers 27 and 31. In this step, the second protective layer 31 is formed by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (siOx) with the thickness of around 2000˜4000 Å. After that, the first to third contact holes 30a, 30b and 30c are formed by selecting removing the first and/or second protective layers 27 and 31 and the gate insulating film 17.
Referring to FIG. 8, the pixel electrode 33 and a transparent electrode 35 are formed on the second protective layer 31 and in the contact holes 30a, 30b and 30c. In this step, the pixel electrode 33 is formed by depositing a transparent conductive material on the second protective layer 31 and the first contact hole 30a, and then patterning it. The pixel electrode 33 is electrically in contact with the drain electrode 25 through the first contact hole 30a. The pixel electrode is formed of any one of ITO, IZO, or ITZO.
The transparent electrode 35 is formed by depositing a transparent conductive material on the second protective layer 31 and the second and third contact holes 30b and 30c, and then patterning it. The transparent electrode 35 is electrically in contact with the storage electrode 29 and the previous gate line 15n-1 through the second and the third contact holes 30b and 30c. 
In the foregoing liquid crystal display, if the TFT turns on, electric charge is accumulated at a storage capacitor and a liquid crystal is driven. The flicker occurring during the operation of the liquid crystal display decreases if the difference (Δ Vp) of a descending voltage upon driving in relation to the accumulated voltage at the storage capacitor is smaller. The fluctuating voltage Δ Vp is decided by the capacitance Cst of the storage capacitor, the capacitance Clc of the liquid crystal, a parasitic capacitance Cgs between the gate electrode 13 and the source electrode 23 of the TFT, and a voltage difference Δ Vg of the pulse applied to the gate electrode 13. The fluctuating voltage Δ Vp is defined as follows according to FORMULA (1).ΔVp=(Cgs/Cst+C1c+Cgs)*ΔVg  (1)
Herein, Cst represents a capacitance of the storage capacitor, Clc represents a capacitance of the liquid crystal, Cgs represents a parasitic capacitance between corresponding gate and source electrodes, and Δ Vg represents a difference in the gate voltage.
According to the FORMULA (1) above, to decrease the fluctuating voltage Δ Vp for reducing flickers, the capacitance Cst of the storage capacitor should be increased, or the capacitor Clc of the liquid crystal or the parasitic capacitance Cgs or the voltage difference Δ Vg of the gate voltage should be decreased. If the capacitance Clc of the liquid crystal, the parasitic capacitance Cgs, and the gate voltage difference Δ Vg are invariable, then at least the capacitance Cst should be increased. And to increase the capacitance Cst of the storage capacitor, the area of the storage electrode needs to be increased. However, an increase of the area of the storage electrode decreases the aperture ratio of the LCD. Particularly, the aperture ratio drops significantly in a ferroelectric LCD that requires a high capacitance Cst of the storage capacitor or in an LCD that requires high precision.
Therefore, there is a need to provide an LCD and its fabrication method that overcome these problems of the related art. Further, there is a need to reduce costs associated with the LCD and its fabrication method by eliminating or reducing the use of expensive masks in fabricating processes of the LCD.